The present disclosure relates to semiconductor memory devices and, more particularly, to flash memory devices.
Flash memory devices as nonvolatile memories are kinds of electrically erasable and programmable read-only memories (EEPROMs) in which plural memory blocks are erased or written with data by one programming operation. A general EEPROM is operable with the feature that one memory block is erasable or programmable at a time. This means that the flash memories operate more rapidly and are effective in reading and writing data when systems employing such flash memory devices read and write data from and into other memory areas at the same time. All kinds of flash memories or EEPROMs are usually configured in a certain structure such that insulation films enclosing charge storage elements used for storing data are inevitably worn out after a specific number of operations.
Flash memories can store information on their silicon chips even without a power supply. More specifically, flash memories are able to retain information without power consumption, even in the interruption of the power supply to the chips. In addition, flash memories offer resistance to physical shocks and fast access times for reading. With those features, the flash memories are widely used as storage units in electronic apparatuses powered by batteries. The flash memories are generally classified in two types, NOR and NAND, in accordance with a logical arrangement of the gates.
In a flash memory device, information is stored in an array of transistors each of which acts as a unit cell storing 1-bit information. On the other hand, there is another kind of flash memory that is advanced in storage capacity, and which is called a multi-level flash memory device that is capable of storing more data bits than a single bit in a unit cell by varying the amount of charges stored in a floating gate of a cell.
A unit cell of the NOR flash memory device is similar to a typical MOSFET in structure, but has two gates. The first one is a control gate that is also included in a general MOSFET, while the second one is a floating gate enclosed by an insulation film. The floating gate is disposed between the control gate and a substrate (or bulk). As the floating gate is isolated from peripheral conductors by the insulation film, electrons are captured in the floating gate to reserve information without leakage. Electrons staying in the floating gate change an electric field from the control gate, partially reducing an effect of the electric field to the substrate, which varies a threshold voltage of the cell. Thus, in reading a data bit from the cell by applying a specific voltage to the control gate, a current may or may not flow through the cell in accordance with the threshold voltage thereof. This operation is regulated by the amount of charges accumulated in the floating gate. Thus, it is able to differentiate data 1 or 0 by detecting whether there is a flow of current through the cell, thereby restoring data stored therein. A multi-level flash memory cell storing more than one bit, detects an amount of current, rather than the presence of current flow, in determining the quantity of electrons accumulated in the floating gate.
A NOR flash memory cell is programmed by applying a program voltage to a control gate, applying a high voltage to a drain, and grounding a source, which sets the cell on a specific data value. With such a bias condition, a large current flows from the drain to the source. This programming scheme is referred to as hot electron injection. In erasing the NOR flash memory cell, a high voltage gap is established between the control gate and the substrate (or bulk), which induces the Fowler-Nordheim (F-N) tunneling effect to release the electrons from the floating gate. A cell array of the NOR flash memory device is usually divided into blocks or sectors each of which forms a segment for erasing. Memory cells belonging to a block are erased at the same time in a single erasing cycle. Otherwise, a programming operation in the NOR flash memory device is carried out in units of bytes or words.
Various ways of erasing data in a NOR flash memory device are proposed in U.S. Pat. No. 5,781,477 entitled “FLASH MEMORY SYSTEM HAVING FAST ERASE OPERATION”, U.S. Pat. No. 5,132,935 entitled “ERASURE OF EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED-CELLS”, U.S. Pat. No. 5,220,533 entitled “METHOD AND APPARATUS FOR PREVENTING OVERERASURE IN A FLASH CELL”, U.S. Pat. No. 5,513,193 entitled “NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CHECKING THE THRESHOLD VALUE OF MEMORY CELLS”, and U.S. Pat. No. 5,805,501 entitled “FLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGIC”, all of which are incorporated by reference in this application.
All memory cells included in a selected sector of a NOR memory device, as shown in FIG. 1, are erased in the sequence of pre-programming, erasing, and post-programming (or over-erasure curing) operations. During the pre-programming operation, the memory cells are programmed in the condition that; sources and bulk are supplied with predetermined voltages, for example, 0V and −1V, respectively; control gates are supplied with a high voltage, for example, a step voltage 2˜8V; and drains are supplied with a positive voltage, for example, 4.2V, to induce hot electrons. According to this bias condition, a sufficient amount of negative charges are accumulated in floating gates of the memory cells, making the floating gates charged with negative potential. This programmed memory cell is referred to as “off-cell”. The programmed memory cells have threshold voltages located in the territory of target threshold voltages corresponding to off-cells.
The pre-programmed memory cells are erased by means of the F-N tunneling scheme. According to the F-N tunneling scheme, a negative voltage, for example, −9V, is applied to the control gates of the cells and a voltage sufficient to cause the effect of F-N tunneling is applied to a semiconductor substrate of the device. During this time, the sources and drains are maintained in floating states. This erasing scheme is referred to as the negative gated bulk erase (NGBE) mode. During the NGBE mode, a strong electric field of about 6˜7 MV/cm is formed between the control gate and the semiconductor substrate, inducing the F-N tunneling effect. As a result of the NGBE mode, negative charges accumulated in the floating gate are discharged into the bulk, that is, into the semiconductor substrate, through an insulation film of about 100 Å thickness. An EEPROM cell erased in this manner is referred to as an “on-cell”. Erased memory cells have threshold voltages located in the territory of the target threshold voltages corresponding to on-cells.
After conducting the NGBE mode, it is checked whether the erased memory cells are located in the range of target threshold voltages in correspondence with the on-cells. In general, there are memory cells having threshold voltages lower than the minimum value of the target threshold voltages range, even after all memory cells have been erased at the same time. A memory cell with such a lower threshold voltage is referred to as an “over-erased memory cell”. These over-erased memory cells may be cured by means of the post-programming (over-erased curing or erasure repairing) operation. As a result, threshold voltages of the over-erased memory cells can be distributed within the territory of target threshold voltages in correspondence with the on-cells.
The post-programming operation is carried out by grounding the sources of the over-erased memory cells, applying a negative voltage, for example, −1V, to the semiconductor substrate, applying a predetermined voltage, for example, 1.6V, to the control gates, and applying a predetermined voltage, for example, 4.2V, to the drains, for a predetermined time. Under this bias condition, negative charges less than those of the pre-programming operation may be accumulated in the floating gate. Therefore, the post-programming operation forces the threshold voltages of the over-erased memory cells to move into the territory of target threshold voltages.
A drain current supplied to a bit line during the post-programming operation, as illustrated in FIG. 2, may leak out through an over-erased memory cell, shown at 10. An amount of current leaking out may be proportional to the number of over-erased memory cells connected with the bit line corresponding thereto. If an amount of leakage current increases, the post-programming operation for selected memory cells may not be carried out in a normal condition. Because of that, it is inevitable to restrict the number of memory cells to be programmed in a time during the post-programming operation. By the restrictive number of memory cells that can be programmed at a time, it may take a long time in conducting the post-programming operation, resulting in an increase in the whole erasing time of the flash memory device.
Therefore, there is a requirement for a new scheme to shorten the time for conducting the post-programming operation.